# Targets

The target device is the **Raspberry Pi 4B** board with a **Broadcom BCM2711 SoC**. This is the same as the target used in \[1]. It features a **quad-core out-of-order ARM Cortex-A72 (ARMv8, 64-bit)** processor, operating at a maximum frequency of 1.8 GHz. This device lacks hardware support for AES. It runs on the Bullseye version of the Raspberry Pi OS (Debian Linux). We execute a C-based unprotected implementation of AES-128 for our experiments without computer optimisations. The considered target is the first round of AES after the AddRoundKey. 

*Note that the traces employed in this challenge differ, rendering the results not directly comparable to those presented in \[1].*

<figure><img src="/files/XVtZWxrhhRb2cW1F3yVT" alt=""><figcaption></figcaption></figure>

## References

1. Harishma Boyapally, Dirmanto Jap, Qianmei Wu, Fan Zhang, and Shivam Bhasin.\
   Reality check on side-channels: Lessons learnt from breaking AES on an ARM cortex\
   a processor. Cryptology ePrint Archive, Paper 2024/1381, 2024. <https://eprint.iacr.org/2024/1381> (accepted in WOOT'25)


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